1. Field of the Invention
The present invention relates to electronics and, more specifically but not exclusively, to circuitry for synchronizing pulses across asynchronous clock domains.
2. Description of the Related Art
This section introduces aspects that may help facilitate a better understanding of the invention. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art.
In electronics, it is not unusual for circuitry operating in one clock domain (referred to herein as the source or input domain) to generate a data signal that needs to be processed by other circuitry operating in another, independent clock domain (referred to herein as the destination or output domain), where independent means that the destination clock may be asynchronous with respect to the source clock and/or have a speed different from that of the source clock, including non-integer multiples of one another. In some applications, the source clock is faster than the destination clock, while the source clock is slower than the destination clock in other applications. Furthermore, in some situations, a data pulse in the input data signal has a duration of one cycle of the source clock, while an input data pulse has a duration longer than one source clock cycle in other situations. Conventionally, two or more different circuits are provided to handle these different applications and/or situations.